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march 2010 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter fan6210 primary-side synchronous rectifier (sr) trigger controller for dual forward converter features ? primary-side trigger controller for dual forward converters with synchronous rectifier (sr) ? specialized sr controller for dual forward converter ? programmable turn-on delay time for the powering sr (rdly pin) ? winding voltage detection for precision control at light-load condition (det pin) ? green-mode operation to improve light-load efficiency ? differential mode control signal with better noise immunity ? v dd over-voltage protection (ovp) applications ? personal computer (pc) power supply ? entry-level server power supply description fan6210 is a primary-side sr trigger integrated circuit (ic) specially designed for the synchronous rectifier (sr) in dual forward converters employing fan6206. fan6210 provides drive signal for the primary-side power switches by using an output signal from pwm controller. fan6210 can be combined with any pwm controller that can drive a dual-forward converter. to obtain optimal timing for the sr drive signals, transformer winding voltage is also monitored. to improve light-load efficiency, green mode operation is employed, which disables the sr turn-on trigger signal, minimizing gate drive power consumption at light load. fan6210 is available in 8-pin sop package. ordering information part number operating temperature range eco status package packing method fan6210my -40c to +105c green 8-pin small outline package (sop) tape & reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 2 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter application diagram figure 1. typical application internal block diagram 3 sin 7 sout 6 vdd + - internal bias 10/8v 5 det + - 1 2 xp xn 100ns controlled rising delay 700ns 300ns one-shot vibrator 300ns rising/falling delay one-shot vibrator one-shot vibrator rising/falling delay 4 rdly rising delay 2/3v 8gnd + - ovp 25.5v green mode (d<10%) gm gm 300ns 50ns 50ns 50ns figure 2. functional block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 3 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter marking information figure 3. top mark pin configuration figure 4. pin configuration pin definitions pin # name description 1 xn pulse signal output terminal for sr off control signal. 2 xp pulse signal output terminal for sr on control signal. 3 sin input signal for high- and low-side gate driver outputs. 4 rdly delay time setting. this delay time is sout rising to trigger xp pulse delay time. 5 det sensing freewheel diode voltage. 6 vdd the power supply pin. 7 sout gate driving to high- and low-side gate driver. 8 gnd ground. f: fairchild logo z : plant code x: year code y : week code tt : package type t: m=sop p : y: green package m : manufacture flow code
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 4 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage 30 v v sin logic input voltage 30 v v sout low side output voltage 18 v v h xp, xn 30 v v l det, rdly 7 v p d power dissipation t a < 50c 400 mw ja thermal dissipation (junction-to-air) 150 c/w t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature (soldering) 10 seconds 260 c esd human body model, jedec:jesd22-a114 4.0 kv charged device model, jedec:jesd22-c101 1.5 kv notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltages, are given with respect to gnd pin. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating ambient temperature -40 +105 c
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 5 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter electrical characteristics v dd =20v, t a =25 , unless otherwise specified. symbol parameter conditions min. typ. max. units vdd section v dd dc supply voltage 7 24 v v dd-on turn-on threshold voltage 9 10 11 v v th-off turn-off threshold voltage 7 8 9 v v dd-ovp v dd over-voltage protection (ovp) 23.0 25.5 28.0 v v dd-ovp-hys hysteresis voltage for v dd ovp 0.3 0.8 1.3 v t ovp v dd ovp debounce time 250 s sin section v sin logic input voltage 10.5 24.5 v t dly_outh delay time between sin-high and sout-high 240 300 350 ns t dly_outl delay time between sin-low and sout-low 75 100 150 ns t on_max sout maximum on time and stop xp pulse 8.5 10.0 12.0 s det section v det_h detect input voltage to send xp after sout falling 2.5 3.0 3.5 v v det_l voltage to drive xp signal after sout falling 1.5 2.0 2.5 v t pd_det delay time to send xp 30 50 100 ns xp xn section t pls_xn high-level pulsewidth of xn signal 250 300 350 ns t pls_xp high-level pulsewidth of xp signal 600 700 800 ns t pd_xn delay time to trigger xn by sin rising or falling edge 25 50 75 ns d pls_off sin duty ratio shorter than d pls_off stop xp pulse 10 % v xn xn signal output voltage level 5.5 8.0 v v xp xp signal output voltage level 5.5 8.0 v t r_xp xp rising time v dd = 15v; c l = 100pf; sout= 1v to 6v 30 ns t f_xp xp falling time v dd = 15v; c l = 100pf; sout= 7v to 2v 30 ns rdly section v rdly rdly voltage r rdly =24k 1.08 1.20 1.32 v t dly_xp delay time to trigger xp by sout rising edge r rdly =24k 280 340 400 ns v z output voltage maximum (clamp) v dd =25v 18.5 v v ol output voltage low v dd =15v; i o = 50ma 1.5 v v oh output voltage high v dd =15v; i o = 50ma 10 v t r sout rising time v dd = 15v; c l = 5nf; sout= 2v to 9v 30 70 120 ns t f sout falling time v dd = 15v; c l = 5nf; sout= 9v to 2v 30 50 100 ns
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 6 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter typical performance characteristics these characteristic graphs are normalized at t a = 25c. 9.0 9.5 10.0 10.5 11.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature v dd-on (v) 8.00 8.25 8.50 8.75 9.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temper atur e v th-off (v) figure 5. turn-on threshol d voltage figure 6. turn-of f threshold voltage 270 290 310 330 350 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t dly_outh (ns) 100 110 120 130 140 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t dly_outl (ns) figure 7. delay time between sin-high and sout-high figure 8. delay time between sin-low and sout-low 260 280 300 320 340 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t pls_xn (ns) 660 680 700 720 740 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t pls_xp (ns) figure 9. high-level pulsewidth of xn signal figure 10. high-level pulsewidth of xp signal 30 40 50 60 70 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t pd_xn (ns) 240 260 280 300 320 340 360 380 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t pls_xp (ns) figure 11. delay time to trigger xn by sin rising or falling edge figure 12. delay time to trigger xp by sout rising edge
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 7 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter function description figure 13 and figure 14 show the simplified circuit diagram of dual-forward converter and its key waveforms. switches q 1 and q 2 are turned on and off together. once q 1 and q 2 are turned on, input voltage is applied across the transformer primary side and power is delivered to the secondary side through the transformer, powering diode d 1 . during this time, the magnetizing current linearly increases. when q 1 and q 2 are turned off, the magnetizing current of the transformer forces the reset diodes (d r1 and d r2 ) and negative input voltage is applied across the transformer primary side. during this time, magnetizing current linearly decreases to zero and the secondary-side inductor current freewheels through diode d 2 . when synchronous rectifiers sr 1 and sr 2 are used instead of diodes d 1 and d 2 , it is important to have proper timing between drive signals for sr 1 and sr 2 . v o d 1 v in q 2 q 1 d 2 l o l m + v x - + v d - i m i lo d r1 d r2 sr 1 sr 2 figure 13. simplified circuit diagram of dual-forward converter figure 14. key waveforms of dual-forward converter figure 15 shows the typical application circuit of fan6210. sin is the gate drive output of the pwm controller. sout is obtained from sin by adding a delay, which is used to drive two switches q 1 and q 2 . the value of the det resistor is recommended as 10k ? and d b is used to block high voltage on winding. the breakdown voltage of zener diode d z is typically 5~6v to protect the det pin from over voltage. q 2 q 1 xp xn sin rdly gnd sout vdd det fan6210 from pwm controller 1 2 3 4 8 7 6 5 v in + - drv drv sn of fan6206 sp of fan6206 d z d b figure 15. typical application circuit figure 16 shows the timing diagrams for heavy-load and light-load conditions. the switching operation of the secondary sr mosfets is determined by the sn and sp signals. fan6206 turns on sr mosfets at the rising edge of the xp signal, while it turns off sr mosfets at the rising edge of xn. within one switching cycle, xp and xn are obtained two times, respectively. the xn signal has a 300ns pulse-width and is triggered by the rising edge and falling edge of the sin signal after a short time delay (t pd_xn ). xp signal has a 700ns pulse-width and is triggered by the rising edge of the sout signal after an adjustable time delay (t dly_xp ) and by the falling edge of the det signal. the relation between the delay resistor (r delay ) and the delay time is shown in figure 17. the triggering of the xp signal by det is prohibited while the xn signal is high. therefore, the xp signal is not triggered at the falling edge of the det signal and is delayed until the xn signal drops to zero at heavy-load condition. at light-load condition, the det falling edge comes after the xn signal drops to zero and the xp signal is triggered at the falling edge of the det signal after a short time delay (t pd_det ).
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 8 fan6210 ? primary-side synchronous rectifier (sr) trigger controller for dual forward converter sin sout det 300ns 100ns 700ns programmable delay 700ns xp xn 50ns 50ns 300ns 50ns 300ns 300ns 50ns 300ns programmable delay gate drive for powering sr gate drive for free-wheeling sr sin sout det 300ns 100ns 700ns programmable delay 700ns xp xn 50ns 50ns 300ns 50ns 300ns 300ns 50ns 300ns programmable delay gate drive for powering sr gate drive for free-wheeling sr heavy load condition light load condition figure 16. timing diagram figure 17. programmable delay with resistor under-voltage lockout (uvlo) the power-on and -off threshold of fan6210 are fixed at 10v and 8v, respectively. the vdd pin can be connected with the power source of the pwm controller. v dd pin over-voltage protection v dd over-voltage protection prevents damage due to abnormal conditions. once the v dd voltage exceeds the v dd over-voltage protection voltage (v dd-ovp ) and lasts for t ovp , fan6210 stops operation . green-mode operation to improve light-load efficiency, green-mode operation is employed, which disables the sr turn-on trigger signal, minimizing gate drive power consumption at light-load condition. green mode is enabled when the duty cycle of sin is smaller than 10%.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 9 fan6210 ? primary-side synchronous rectifier (sr) trigger for dual forward converter typical application circuit (dua l forward converter with sr) application fairchild devices input voltage range output pc power fan480x fan6210 fan6206 90~264v ac 12v/24.5a rdly det xp gnd sin vin vo=12v 1 2 3 4 8 7 6 5 xn sout vdd opwm (from fan480x) pfc stage vac from vdd of fan480x ipwm (to fan480x) 4.7 4.7 1n4148 1n4148 10k 10k 10k 1n4148 1n4148 1n4148 1n4148 1n4148 10k 8.2k uf1007 uf1007 fr107 10k zd/5.6v 470 0.15 100nf 470pf fcp20n60 fcp20n60 105k 10k 10k 73uh 1.8uh 3300uf 3300uf 3k 1k 1uf 38.3k 10k (primary 300uh) 1:1.2 1:1 (160uh) 74:7 1:1.2 tl431 pc817 10 10 sp vdd lpc1 gate1 sn 1 2 3 4 8 7 6 5 lpc2 gnd gate2 68k 2k 100nf figure 18. application circuit
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 10 fan6210 ? primary-side synchronous rectifier (sr) trigger for dual forward converter physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 19. 8-pin small out-line package (sop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6210 rev. 1.0.2 11 fan6210 ? primary-side synchronous rectifier (sr) trigger for dual forward converter

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